Atari-ST(E) in a Chip

Atari ST another Approach for this Machine: “Suska”

Who does not know this vintage home computer from former times? Beside Altair, Commodore, Sinclair, Dragon, Tandy and others was there also Atari with its successful ST series. This project implements the hardware of these Atari machines in an FPGA. This is done by providing individual function groups in the programming language VHDL. The result is then a so-called IP core (IP stands for Intelectual Property), an abstract description of the entire system, which can be implemented on almost any arbitrary FPGA. This IP core is not by the way to be confusued with a program. It describes hardware and therefore is designated as a configuration. The hardware model is sectioned into the Custom chips GLUE, MMU, Shifter, DMA (Direct Memory Access) and naturally the 68000 CPU fom Motorola efficient for conditions. The project still is in an early alpha stage. Anyone who would like to contribute their own VHDL knowledge is very welcome. The following table summarizes the current approximate status. The numbers indicated here refer to a first executable draft with all STE characteristics.

All began in spring 2003 with this hardware (which is by the way still today in operation). On the left picture you can see, that the GLUE chip is pulled out means the GLUE IP core is under development.

Since it is boring to work just on one site, the Shifter chip was the next candidate of choice. Pulled out and go …

Ok, ok, this is not really looking like a high end video system. But this first Shifter implementation seems to have something common with a green desktop – may we hope?

Going on … after a couple of long nights and a few more pints of beer, the Shifter behavior turns into something similar like a ‘normal’ video output:

So, look at this. Here you can see the video output connected to my favourite monitor, the SC124. The work on the shifter last about two and a half weeks, coming to this first reasonable version. Problems appeared with a lateral shift of the whole screen, a topic which could be solved the long time of one and a half years later.

The interaction between GLUE, MCU and DMA turned out as a complex thing. Especially the DMA unit, which’s control is split between GLUE and MCU did require a lot of patience and nerves. During the modelling of the DMA unit, the used floppy disks had to be reformatted on a PC about 470 times because the DMA write access shreddered all the information including the format data. The same happened to the connected hard drive (by the way a Megafile 60). But at any time the work was done and after a lot of unsuccessful attempts, reading, writing and formatting floppies and the harddrive gave a pleasure. This first milestone was achieved in the beginning of the year 2005.

This picture shows the work on the DMA during this strenuous development phase. The MCU and the DMA are pulled out of their sockets. The DMA is in progress while the VHDL-MCU seems to work fine. The GLUE is up to now too buggy to replace it by the IP core.

Since this time a complete implementation of the whole STE machine into one single FPGA got more and more into the scope of feasibility. Later works on the Blitter, the Shadow video controller of the Stacy or STBook or the floppy disk formatter WD1772 turned out long-winded but straight ahead and solvable. The IP core of the computer with all under ’Project’s Progress’ mentioned Chips without the CPU was firstly released in June 2006. The first publicly available version of the VHDL modelling is 2K6A.